Via etch method for back contact multijunction solar cells

ABSTRACT

This disclosure relates to semiconductor devices and methods for fabricating semiconductor devices. Particularly, the disclosure relates to back-contact-only multijunction solar cells and the process flows for making such solar cells, including a wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers.

This application is a Divisional of U.S. application Ser. No.15/332,036, filed on Oct. 24, 2016, which claims the benefit under 35U.S.C. § 119(e) of U.S. Provisional Application No. 62/286,100 filed onJan. 22, 2016, which is incorporated by reference in its entirety.

FIELD

This disclosure relates to semiconductor devices and methods forfabricating semiconductor devices. Particularly, the disclosure relatesto back-contact-only multijunction solar cells and the process flows formaking solar cells, including a wet etch process that removessemiconductor materials non-selectively without major differences inetch rates between heteroepitaxial III-V semiconductor layers.

BACKGROUND

Conventional multi junction solar cells have been widely used forterrestrial and space applications because of their high efficiency.Multijunction solar cells (100), as shown in FIG. 1, include multiplediodes in series connection, known in the art as junctions or subcells(106, 107, and 108), realized by growing thin regions of epitaxy instacks on semiconductor substrates. Each subcell in a stack possesses aunique bandgap and is optimized for absorbing a different portion of thesolar spectrum, thereby improving efficiency of solar energy conversion.These subcells are chosen from a variety of semiconductor materials withdifferent optical and electrical properties in order to absorb differentportions of the solar spectrum. The materials are arranged such that thebandgap of the subcells becomes progressively narrower from the topsubcell (106) to the bottom subcell (108). Thus, high-energy photons areabsorbed in the top subcell and less energetic photons pass through tothe lower subcells where they are absorbed. In every subcell,electron-hole pairs are generated and current is collected at ohmiccontacts in the solar cell. Semiconductor materials used to form thesubcells include, but are not limited to, germanium and alloys of one ormore elements from group III and group V on the periodic table. Examplesof these alloys include, but are not limited to, indium galliumphosphide, indium phosphide, gallium arsenide, aluminum galliumarsenide, indium gallium arsenide, and dilute nitride compounds. Forternary and quaternary compound semiconductors, a wide range of alloyratios can be used.

Solar cells are manufactured on a wafer scale using conventionalsemiconductor processing methods known to practitioners skilled in theart. Danzilio (CS MANTECH Conference, May 14-17, 2007, Austin, Tex., pp.11-14) summarizes the processing steps for making a typicalmultijunction solar cell.

A through-wafer via (TWV) is an electrical interconnect between the top(front) and bottom (back) surfaces of a semiconductor chip. TWVs areroutinely used for a variety of applications in the field ofsemiconductor devices including solar cells. FIG. 2A and FIG. 3A showexamples of TWVs (200 and 300) for solar cells with front and backcontacts. TWVs are electrically isolated from the solar cell substrate(202 and 302) and all the epitaxial regions (203 and 303), and areelectrically connected to the patterned cap regions (204 and 304). Thepatterned cap regions are patterned such that they surround the TWVstructures on the top surface of the solar cell. Front side metal pads(201 and 301) lay over patterned cap regions (204 and 304). TWVs alsocomprise back side metal (205 and 305), via metal (206 and 306),passivation layer (207 and 307), via contact metal region (208 and 308)and gap 209 between passivation layer 207 and back side metal 205. Insome known examples of TWVs, a recess structure 309 is present in theTWV design. Methods to fabricate TWVs are known to practitioners skilledin the art of semiconductor fabrication. For example, Chen et al.(Journal of Vacuum Science and Technology B, Volume 27, Issue 5, p.2166-2009) disclose a semiconductor device with TWVs for a high mobilityelectron transport device application.

TWVs are also used to provide back-contact packaging in solar cells.Back-contact cells have both positive and negative external contact padsdisposed on the back surface, which allows for optimized moduleefficiency by increasing the packing density of solar cells. Shadinglosses and resistive losses are also significantly reduced. VanKerschaver et al. (Progress in Photovoltaics: Research and Applications2006; 14:107-123) summarizes several approaches for back-contact solarcells.

Dry etching is a routine method used in semiconductor fabrication whichhas found limited use in solar cell manufacturing. Dry etching involvesthe removal of semiconductor material by exposing the material to plasmaof reactive gases in a vacuum chamber. Dry etching of heteroepitaxiallayers in multijunction solar cells involves added complexity becauseeach class of semiconductor material requires a unique etch condition.This complexity causes a slower net etch rate and a bottleneck inmanufacturing. As etching proceeds across multiple layers ofheterogeneous semiconductor materials, re-deposition of etched-offmaterial causes rough sidewalls and is unavoidable. A mask is used toprotect wafer areas where etching is not required. A photosensitivepolymer is typically used as the mask, but a photosensitive polymer maskcannot withstand the long etch times and high heat required for dryetching. The photosensitive polymer mask is often destroyed, leading topitting and significantly to the generation of rough surfaces, whichcomplicates subsequent sidewall passivation processing and decreasesreliability of manufactured devices. FIG. 4A depicts a schematic of awafer cross-section imaged by scanning electron microscopy, damaged withpitting and rough sidewall surfaces (408 and 409). The device shown inFIG. 4A includes cover glass 407, front side metal pad 406, ARC 405,heteroepitaxial layer 403, substrate 402, patterned cap regions 404, andback side 401 of substrate 402. The sidewall 409 of heteroepitaxiallayer 403 is characterized by a rough surface including pitting and/orundercutting resulting from the dry etch. Pitting 408 is also shown onthe back side surface 401 of substrate 402, which can also be caused bythe dry etch. Alternative masking methods such as dielectric hard maskscan be used in place of a photosensitive polymer, but these masksrequire elaborate downstream steps for removal from the wafer. Dryetching also involves expensive equipment setup and maintenance. Insummary, dry etching involves the following complications:

-   -   1. electroplating or electrografting to protect wafer areas        where etching is not desired, requiring expensive and specific        equipment;    -   2. low processing throughput and longer processing time because        dry etching can be carried out on only a few wafers at a time;    -   3. difficulty in controlling etch rate as well as etch stop,        leading to insufficient etching or over-etching;    -   4. uneven etching of heteroepitaxial III-V semiconductor layers        results in pitting and rough sidewall surfaces, which complicate        subsequent sidewall passivation;    -   5. higher possibility of device failure due to insufficient        sidewall passivation;    -   6. more chemical, water, and energy consumption during        fabrication; and    -   7. higher cost from equipment procurement and maintenance.

Wet etching, another method for removing semiconductor material by usingchemicals in liquid phase, is not without shortcomings. Typically, wetetchants used for etching one class of semiconductor materials isselective and will not etch certain other classes of semiconductormaterials. A comprehensive list of wet etchants, etch rates andselectivity relationships was published by Clawson, Materials Scienceand Engineering, 31 (2001) 1-438. The selectivity of a wet etchant mayalso depend on alloy concentration of the compounds. Consequently,etching heteroepitaxial layers can require application of multiple wetetch chemistries. Using multiple applications of different wet etchantsdue to selectivity typically results in jagged, non-smooth, and/orirregular through-wafer via sidewalls (as shown in FIG. 4A). This isobserved in solar cell fabrication where different etch chemistries areused for each class of semiconductor material in the heteroepitaxiallayers, resulting in distinctively different etch profiles and roughsidewall surfaces throughout the wafer. Zaknoune et al., J. Vac. Sci.Technol. B 16, 223 (1998) reported a wet etching method that isnonselective for III-V phosphides and arsenides as an alternative tousing multiple wet etchants. Although the method is nonselective, theetching of gallium arsenide results in very rough morphology andinvolves an etch rate 10 times greater than the etching of aluminumgallium indium phosphide. Zaknoune et al. describes a system with onelayer of epitaxy, such as that found in heterojunction bipolartransistors (HBT), quantum well lasers (QWL) and high electron mobilitytransistors (HEMT). The Zaknoune et al. method does not address anysidewall problem related to heteroepitaxial layers that ischaracteristic of multijunction solar cells.

Typically, rough/jagged through-wafer via sidewalls complicatesubsequent sidewall passivation, leading to an increase in devicefailures and lower fabrication yield. In addition, the use of multipleetchants has other disadvantages compared to single-etch chemistries,including, for example:

-   -   1. increased difficulty in controlling the etch rate and        undesirable lateral undercutting of layers;    -   2. uneven etching of different semiconductor layers and        increased difficulty in subsequent sidewall passivation        processing;    -   3. higher possibility of device failure due to insufficient        sidewall passivation;    -   4. longer processing time due to complications and        unpredictability inherent in the method;    -   5. more chemical, water, and energy consumption during        fabrication; and    -   6. more chemical waste generation.

The abovementioned conventional processes have hindered cost-effectivefabrication of multijunction solar cells. There were attempts to explorenon-selective etchants and a couple examples are briefly described.Zaknoune et al. (J. Vac. Sci. Technol. B 16, 223, 1998) reports anetching procedure that is nonselective for gallium arsenide and aluminumgallium indium phosphide, where the aluminum gallium indium phosphidequaternary compound has 35% aluminum phosphide, 15% gallium phosphide,and 50% indium phosphide. The etching procedure described by Zaknoune etal. uses a diluted solution of hydrochloric acid, iodic acid, and waterto etch 300 nm of the quaternary compound grown on a gallium arsenidesubstrate using a photosensitive polymer mask. The main applicationareas described in the paper by Zaknoune et al, are heterojunctionbipolar transistors (HBT), various quantum well lasers (QWL), and highelectron mobility transistors (HEMT) for which large conduction andvalance band discontinuities are required. These devices are majoritycarrier devices in which the large bandgap materials are typically usedas barrier materials for majority carriers. Zaknoune et al. describes asystem with one layer of epitaxy and do not recognize any sidewallproblem related to multilayer epitaxy that is characteristic of solarcells.

The device requirements for multijunction solar cells are significantlydifferent than for HBTs, QWLs, and HEMTs, largely because multijunctionsolar cells are minority carrier devices. Consequently the proceduredescribed by Zahnoune et al. has no direct application to etchingmultijunction solar cell structures, which include a wide variety ofsemiconductor materials with a wide range of bandgaps (for example, from0.67 eV to 2.25 eV).

The present disclosure describes a TWV fabrication method that overcomescomplications with existing methods. The various advantages include thefollowing:

-   -   1. when anti-reflective coating (ARC) is deposited, as part of        routine solar cell fabrication, a pattern is added where the TWV        is to be constructed, i.e. the ARC is used as a dielectric etch        stop between the semiconductor and the metal pads on top of the        wafer. This additional function of ARC simplifies TWV        fabrication by eliminating the application of an extra etch        stop;    -   2. standard manufacturing processing steps are employed,        including photolithography, wet etching and thin film        evaporation;    -   3. significant cost reduction due to the use of inexpensive        equipment, chemicals and methods;    -   4. processing throughput is higher because multiple wafers can        be etched at the same time and fewer etching process steps are        required;    -   5. areas of wafer that need to be protected from etching can be        protected by a photosensitive polymer, employing a lower cost        material and simpler method than electroplating photoresist or        electrografting;    -   6. smooth, 100% passivated TWV walls, which improves        manufacturing yield by lowering the risk of device failure; and    -   7. a thinner substrate results from these processing steps,        making the solar cells lighter and appropriate for space        applications.

SUMMARY

According to the present invention, methods of forming a semiconductordevice are disclosed, comprising the steps of: providing a semiconductorwafer, wherein the semiconductor wafer comprises: a substrate regioncomprising a front side and a back side; a heteroepitaxial layeroverlying the front side of the substrate region, wherein, theheteroepitaxial layer comprises a first subcell and at least oneadditional subcell overlying the first subcell; and at least one of thefirst subcell or the at least one additional subcell comprises an alloycomprising one or more elements from group III of the periodic table, N,As, and an element selected from Sb, Bi and a combination thereof; aplurality of patterned cap regions overlying the heteroepitaxial layer;an anti-reflective coating overlying the heteroepitaxial layer; and; acorresponding metal region overlying each of the plurality of patternedcap regions; bonding a cover glass to the front side of thesemiconductor wafer with an optically clear adhesive; removing a desiredamount from the semiconductor wafer by a thinning of the substrateregion from the back side of the semiconductor wafer; patterning theback side of the semiconductor wafer with a back etch through-wafer viapattern; etching from the back side of the semiconductor wafer aplurality of through-wafer vias using a single wet etchant mixture,wherein each of the plurality of through-wafer vias extends from theback side of the semiconductor wafer to the anti-reflective coatingoverlying the heteroepitaxial layer; removing the anti-reflectivecoating to expose a bottom side of the corresponding metal region with asubsequent wet etching method, wherein the subsequent wet etching methodis specific for the removal of the anti-reflective coating; depositing apassivation liner on the through-wafer via walls with standarddeposition techniques; depositing a resist pattern on the back side ofthe semiconductor wafer for back side metal isolation, wherein theresist pattern underlays the passivation liner; depositing a metal onthe back side of the semiconductor wafer and on the through-wafer via;and removing the resist pattern and a sacrificial metal.

According to the present invention, methods of forming a semiconductordevice are disclosed, comprising the steps of: providing a semiconductorwafer, wherein the semiconductor wafer comprises: a substrate regioncomprising a front side and a back side; a heteroepitaxial layeroverlying the front side of the substrate region, wherein, theheteroepitaxial layer comprises a first subcell and an at least oneadditional subcell overlying the first subcell; at least one subcellcomprises an alloy comprising one or more elements from group III of theperiodic table, N, As, and an element selected from Sb, Bi and acombination thereof; and a cap layer overlying the heteroepitaxiallayer; patterning the front side of the semiconductor wafer with a frontetch through-wafer via pattern; etching from the front side of thesemiconductor wafer a plurality of through-wafer vias using a single wetetchant mixture, wherein, each of the plurality of through-wafer viasextends from the front side surface of the semiconductor wafer into thesubstrate; patterning the plurality of patterned cap regions on theheteroepitaxial layer on the front side of the semiconductor wafer;depositing an anti-reflective coating overlying the heteroepitaxiallayer and the through-wafer via sidewalls; removing, from the frontside, the anti-reflective coating from the bottom of the through-wafervia holes; depositing a front side resist pattern from the front side ofthe semiconductor wafer, wherein the front side resist pattern guidesmetal layer lithography; and depositing a metal on the front side of thesemiconductor wafer, on the through-wafer via sidewalls and on thethrough-wafer via bottom.

According to the present invention, semiconductor devices are disclosedcomprising: a heteroepitaxial layer, further comprising an alloycomprising one or more elements from group III of the periodic table, N,As, and an element selected from Sb, Bi and a combination thereof; and aplurality of through-wafer vias characterized by the absence of pittingon smooth sidewall surfaces formed by a method provided by the presentdisclosure.

According to the present invention, through-wafer via structures aredisclosed comprising: a substrate comprising a back side and a frontside; a heteroepitaxial layer overlying the front side of the substrate;an antireflection coating overlying a first portion of theheteroepitaxial layer; a patterned cap region overlying a second portionof the heteroepitaxial layer; a front side metal pad overlying andelectrically connected to the patterned cap region, wherein the frontside metal pad comprises a bottom surface; and a through-wafer viaextending from the back side of the substrate to the front side metalpad, wherein the through-wafer via comprises sidewalls; a passivationliner overlying a portion of the back side of the substrate and thesidewalls of the through-wafer via; and a metal layer overlying thepassivation liner and the bottom surface of the front side metal padwithin the through-wafer via.

According to the present invention, through-wafer via structures aredisclosed comprising: a substrate comprising a back side and a frontside; a heteroepitaxial layer overlying the front side of the substrate;an anti-reflection coating overlying a first portion of theheteroepitaxial layer; a patterned cap region overlying a second portionof the heteroepitaxial layer; a front side metal overlying a portion ofthe anti-reflection coating and the patterned cap region; athrough-wafer via extending from the back side of the substrate througha portion of the anti-reflection coating; a passivation liner overlyingside walls of the through-wafer via; a metal seed layer overlying thepassivation liner and plugging the bottom of the through-wafer via; anda metal overlying the metal seed layer and filling the through-wafervia.

According to the present invention, semiconductor devices are disclosedcomprising a through-wafer via structure provided by the presentdisclosure.

According to an aspect of the invention, a through-wafer via structurecomprises: a substrate having a front substrate surface and a backsubstrate surface; a heteroepitaxial layer overlying the front substratesurface; a front surface contact overlying a portion of and electricallyconnected to the heteroepitaxial layer; an optical adhesive overlyingthe front surface contact and the heteroepitaxial layer; a coverglassoverlying the optical adhesive; a back surface solder pad underlying aportion of and electrically connected to the back substrate surface; afront surface solder pad underlying and insulated from the backsubstrate surface; and a through-wafer-via interconnecting the frontsurface solder pad and the front surface contact.

According to an aspect of the invention, a semiconductor devicecomprises a plurality of the through wafer via structures according tothe invention.

According to an aspect of the invention, a method of fabricating athrough wafer via structure, comprises: providing a semiconductor wafer,wherein the semiconductor wafer comprises: a substrate comprising afront substrate surface and a back substrate surface; a heteroepitaxiallayer overlying the front substrate surface; a front surface contactoverlying and electrically connected to a portion of the heteroepitaxiallayer; an optical adhesive overlying the front surface contact and theheteroepitaxial layer; and a coverglass overlying the optical adhesivelayer; and thinning the substrate.

According to an aspect of the invention, a through wafer via structurecomprises: a substrate having a front substrate surface and a backsubstrate surface; a heteroepitaxial layer overlying the front substratesurface; a front surface contact overlying a portion of and electricallyconnected to the heteroepitaxial layer; an optical adhesive overlyingthe front surface contact and the heteroepitaxial layer; a coverglassoverlying the optical adhesive; a passivation layer underlying a portionof the back substrate surface; a back metal pad underlying a portion ofthe passivation layer; a through-wafer-via electrically interconnectingthe front metal contact and the back metal pad; and a backside metalelectrically connected to the back substrate surface.

According to an aspect of the invention, a semiconductor devicecomprises a plurality of the through wafer via structures according tothe invention.

According to an aspect of the invention, a method of fabricating athrough wafer via structure comprises: providing a semiconductor wafer,wherein the semiconductor wafer comprises: a substrate having a frontsubstrate surface and a back substrate surface; a heteroepitaxial layeroverlying the front substrate surface; and a patterned cap regionoverlying a first portion of the heteroepitaxial layer; etching athrough-wafer-via extending from the heteroepitaxial layer to within thesubstrate; depositing an antireflection coating on a second portion ofthe heteroepitaxial layer and on a sidewall and a bottom of thethrough-wafer-via; etching the antireflection coating on the bottom ofthe through-wafer-via to expose the substrate; depositing a frontsurface contact overlying at least a portion of the patterned capregion, the antireflection coating within the patterned cap region, thesidewalls of the through-wafer-via, and the bottom of thethrough-wafer-via; applying an optical adhesive overlying the frontsurface contact, the patterned cap region, and the antireflectioncoating; applying a coverglass overlying the optical adhesive; andthinning the substrate.

BRIEF DESCRIPTION OF DRAWINGS

The drawings described herein are for illustration purposes only. Thedrawings are not intended to limit the scope of the present disclosure.

FIG. 1 is a cross-section of a multijunction solar cell.

FIG. 2A is a cross-section of a multijunction solar cell with TWVsfabricated by dry etching.

FIG. 2B shows a bottom view of the multijunction solar cell s shown inFIG. 2A.

FIG. 3A is a cross-section of a multijunction solar cell with TWVsfabricated by dry etching.

FIG. 3B shows a bottom view of the multijunction solar cell shown inFIG. 3A.

FIG. 4A is a schematic cross-section of a semiconductor waferrepresentative of a scanning electron microscopy image illustratingwafer damage caused by current methods.

FIG. 4B is a schematic cross-section of a semiconductor waferrepresentative of a scanning electron microscopy image fabricated usingmethods provided by the present disclosure.

FIGS. 5-14 illustrate a process flow for certain embodiments provided bythe present disclosure.

FIG. 15 is a cross-section of a multijunction solar cell with a TWVfabricated using the method illustrated in FIGS. 5-14.

FIG. 16A is a top view of the multijunction solar cell shown in FIG. 15.

FIG. 16B is a bottom view of the multijunction solar cell shown in FIG.16.

FIGS. 5 and 17-26 illustrate a process flow for certain embodimentsprovided by the present disclosure.

FIG. 27 is a cross-section of a multijunction solar cell with a TWVfabricated using the method illustrated in FIGS. 5 and 17-26.

FIG. 28 shows a cross-sectional view of a multijunction solar cell witha TWV fabricated using a dry etch.

FIGS. 29A-29C show cross-sectional views of TWVs fabricated using a dryetch.

FIGS. 30A-30C shows cross-sectional views of a multijunction solar cellwith a TWV fabricated using a wet etch method provided by the presentdisclosure.

Reference is now made in detail to certain embodiments of the presentdisclosure. While certain embodiments of the present disclosure aredescribed, it will be understood that it is not intended to limit theembodiments of the present disclosure to the disclosed embodiments. Tothe contrary, reference to embodiments of the present disclosure isintended to cover alternatives, modifications, and equivalents as may beincluded within the spirit and scope of the embodiments of the presentdisclosure as defined by the appended claims.

DETAILED DESCRIPTION

Single step wet etch processes are described to create a semiconductordevice that requires back contacts. Specifically, TWVs for back-contactmultijunction solar cells are fabricated with this wet etch method. TWVsare fabricated that are electrically isolated from the solar cellsubstrate and all epitaxial regions, except for the patterned capregions. The method of wet etch chemistry employed removingsemiconductor materials non-selectively without major differences inetch rates between different heteroepitaxial layers. This is useful formultijunction solar cells, which comprise multiple heterogeneoussemiconductor layers epitaxially grown on the semiconductor substrate.Multijunction solar cells thus formed lack pitting on the wafer surfacesand on the TWV sidewalls, and have smooth sidewall surfaces within theTWVs. This process employs standard wafer batch processing,significantly reduces fabrication complexity and cost, increasesprocessing throughput, and improves device performance and reliabilityby ensuring complete passivation of TWV walls.

The process steps described herein can be modified or adapted providedthat the removal of semiconductor material in exposed areas is achievedusing a single-step wet etch process. It is to be understood thatadditional process steps inserted in all semiconductor processes thatrequire TWV fabrication.

In certain aspects of the invention, TWVs can be etched from the backside of a semiconductor wafer. The semiconductor wafer has front sidemetal pads, patterned cap regions, metal regions that lay over eachpatterned cap region, and an ARC that result from front side waferprocessing. The front side of the semiconductor wafer can also be bondedto cover glass with an optically clear adhesive. The semiconductor canbe thinned from its back side. TWV holes can be etched from the backside of the semiconductor wafer so that the TWVs extend from the backside surface of the semiconductor wafer to the ARC overlying the top ofthe heteroepitaxial layer. Wafer areas, where etching is not desired,can be protected by resist patterns. Then, multiple layers ofsemiconductor material can be wet etched where TWVs are desired; etchingcan be carried out in a single step with wet chemistry that may comprisethe use of an iodic acid-hydrochloric acid mixture. The ARC can serve asa dielectric etch stop and can protect the front side metal pad frombeing etched. The ARC can then be removed to expose the bottom side ofthe front metal pads. A passivation layer can subsequently be depositedover the smooth TWV sidewalls. This can be followed by the deposition ofa metal isolation resist pattern, protecting semiconductor wafer areaswhere metal is not required. Then, metal can be deposited on the bottomof the TWV and on the sidewalls of the TWV and on the back side of thewafer. Finally, the metal isolation resist pattern and sacrificial metalcan be removed.

In another aspect of the invention, TWVs can be etched from the frontside of a semiconductor wafer. The semiconductor wafer has a cap layeroverlying the heteroepitaxial layer. TWV holes can be etched from thefront side of the semiconductor wafer into the substrate layer using asingle-step wet chemistry that may include—the use of an iodicacid-hydrochloric acid mixture. Wafer areas where etching is not desiredcan be protected by resist patterns. Then, patterned cap regions can beformed from the cap layer. ARC, which functions as a passivation layer,can be applied on the front side of the semiconductor wafer on regionssurrounding the patterned cap regions as well as on the smooth surfacesof the TWV holes. The ARC that lines the bottom surface of TWV holes canbe removed to expose the substrate. Then, metal can be deposited on theTWVs and on the front side of the semiconductor wafer, except onsemiconductor wafer areas where metal is not desired and thesemiconductor wafer can be protected by another resist pattern. Thisresist pattern can be removed and gold can be deposited to fill theTWVs. Gold can be deposited by electroplating. The semiconductor wafercan be mounted on cover glass with optically clear adhesive. Then, fromthe back side, the semiconductor wafer can be thinned and a passivationlayer can be patterned onto this back side surface with a hard bakingstep. This can be followed by metal deposition, guided by a metalisolation resist pattern, on the back side of the semiconductor wafer.Finally, the metal isolation resist pattern and sacrificial metal can beremoved.

Semiconductor devices formed using the single-step wet etch processesdescribed lack pitting on the wafer surfaces as well as on the TWVsidewalls. Pitting morphology is typical if dry etching is employed tofabricate TWVs. The TWV sidewalls fabricated by this single-step wetetch method also have significantly smooth sidewall surfaces.Semiconductor devices formed by this method include back-contact-onlymultijunction solar cells.

SEM (scanning electron microscopy) images showing cross-sections of TWVsfabricated using dry etch methods and fabricated using wet etch methodsprovided by the present disclosure are provided in FIGS. 28-30.

FIG. 28 shows a cross-section schematic view of a multijunction solarcell structure with a TWV fabricated using a dry etch process, includingback side via metal 2801, passivation layer 2802, GaAs substrate 2803,bottom subcell 2804, middle subcell 2805, top subcell and contact layers2806, adhesive 2807, and cover glass 2808. The surface of the GaAssubstrate is characterized by pitting due to compromise of the etchmask. The side wall of the via is also rough and pitted. The roughsurface result in the passivation layer is not completely conformal. Thepurpose of the passivation layer is to electrically isolate the TWVmetal from the semiconductor layers such as the substrate and theheteroepitaxial layers. A high quality passivation layer will beconformal to the underlying layer such as the substrate and the sidewall of the TWV and will be free of pinholes. In FIG. 28 there is poorpassivation over the sharp edges of the side walls and the pits in thesubstrate can reach the heteroepitaxial layers.

FIGS. 29A-29C also show cross-sections of TWV vias fabricated using dryetch methods. FIG. 29A shows electroplated back side metal 2901,passivation layer 2902, GaAs substrate 2903, bottom subcell 2904, middlesubcell 2905, top subcell and contact layers 2906, adhesive 2907, coverglass 2908, and top side metal pad 2909. There is no passivation on therough side wall surfaces. FIG. 29B shows that dry etching can producesmooth side walls in a GaAs substrate; however, as shown in FIG. 29C, adry etch of both GaAs and a heteroepitaxial layer produces rough sidewall surfaces that are difficult to passivate. FIG. 29C shows both across-sectional and a top view of a TWV structure of GaAs andheteroepitaxial layers.

For the dry etch TWV structures, because the post-etch substrate and viawall topography is rough and/or pitted, the passivation layer coatingquality is poor, especially around the via edges where the passivationthickness is less than 1 μm and there are a large number of pinholes inthe passivation layer. These points serve as a source for electricalshorting. Dry etching also generates etch mask residue such as burnedresist that cannot be removed from the wafer without employing harshcleaning and processing methods that would compromise the via structure.The burned resist results from the prolonged dry etch of the III-Vheteroepitaxial stack and tends to accumulate around the TWV openingsand also contributes to the formation of pinholes in the passivationcoating.

FIGS. 30A-30C show cross-sectional views of TWVs prepared using wet etchmethods provided by the present disclosure. FIG. 30A shows depositedback side metal 3001, passivation layer 3002, GaAs substrate 3003,bottom subcell 3004, middle subcell 3005, top subcell and contact layers3006, optically clear adhesive 3007, cover glass 3008, and ARC etch stop3009. As shown in FIG. 30A, the top surface of the substrate and theside wall of the TWV are smooth and free of pitting and undercutting.The passivation layer conformably coats the surfaces that were etchedusing the iodic acid wet etch method provided by the present disclosure.The wet etched surfaces can comprise traces of iodine. FIG. 30B shows across section with some lateral undercutting of the heteroepitaxiallayer but with sufficiently smooth surfaces that the passivation layerconformally coats the side wall of the TWV. FIG. 30C shows another viewof a TWV structure fabricated using the iodic acid wet etch methodprovided by the present disclosure. FIG. 30C also shows the bottom ofthe via metal in the TWV structure. The passivation thickness is 3 μm atthe edges of the TWV. As shown in these figures, because the substrateand TWV surfaces are smooth and free of post-etch contamination, thepassivation coating quality is high and is 100% conformal.

In the following detailed description, reference is made to theaccompanying drawings that illustrate specific embodiments.

As shown in FIG. 1, multijunction solar cells 100 can include asubstrate 5, back metal contact 52, top metal contact 2 including capregions 3 and heteroepitaxial layers 45 forming the subcells. Themultijunction solar cell in FIG. 1 includes three subcells 106, 107, and108. Each subcell can comprise a front surface filed 4 and emitter 102forming element 132, depletion region 103, base 104, back surface field105, and tunnel junction 167. An ARC can cover the top surface of themultijunction solar cell.

At least one of the subcells can comprise a dilute nitride subcell.Examples of dilute nitride subcells include GaInNAsSb, GaInNAsBi,GaInNAsSbBi, GaNAsSb, GaNAsBi, and GaNAsSbBi.

The process flow described herein is merely an example. Other processflows with different steps can be used to achieve TWVs on semiconductormaterial such as multijunction solar cells.

FIGS. 5-15 illustrate an aspect of the invention that associated withetching TWVs from the back side of a semiconductor wafer in thefabrication of a back-contact solar cell. FIGS. 5-8 show steps involvedin front side processing. FIGS. 8-15 show steps associated with backside processing, including the wet etch steps provided by the presentdisclosure. The process steps and final product described can bemodified by one skilled in the art to accommodate a wide variety ofsemiconductor devices; the steps and final product are not limited tosolar cells and are applicable to other semiconductor devices and inparticular to minority carrier devices. The semiconductor wafercross-sections shown in FIGS. 5-15 can be summarized as follows: FIG. 5shows a heteroepitaxial layer on an unmodified substrate; FIG. 6 shows awafer after contact cap layer patterning; FIG. 7 shows a wafer followingapplication of an ARC; FIG. 8 shows a wafer following application of afront side metal pad; FIG. 9 shows a wafer after wafer bonding,back-grinding and wet etch back-thinning; FIGS. 10A and 10B show a waferafter via hole lithography and wet etch; FIG. 11 shows a wafer after viaetch stop (ARC/dielectric) removal; FIG. 12 shows a wafer afterpassivation layer patterning and hard bake; FIG. 13 shows a wafer afterback side and via-metal isolation lithography; FIG. 14 shows a waferafter back side and TWV-metal deposition; and FIG. 15 shows a completeddevice after metal lift off (TWV metal and back side metal separation.)

A semiconductor wafer can first undergo front side processing (FIGS.5-8). As shown in FIG. 5, a semiconductor wafer can comprise a substratelayer 505 and the back side 506 of the wafer, and a heteroepitaxiallayer 504 overlying the substrate layer 505. Materials used to form thesubstrate include, for example, germanium, gallium arsenide, alloys ofgermanium, and alloys of gallium arsenide. Materials used to form theheteroepitaxial layer include, for example, alloys of one or moreelements from group III and group V on the periodic table, such asindium gallium phosphide, indium phosphide, gallium arsenide, aluminumgallium arsenide, indium gallium arsenide, and dilute nitride compounds.FIGS. 5-6 show cap region 502 and patterned cap regions 602A that areformed on the front side of the semiconductor wafer, overlying theheteroepitaxial layer (504 and 604). The patterned cap regions 602A maybe patterned in a disk shape, but can also be patterned in a variety ofgeometric configurations, as well as shaped to function as gridlines,busbars, pads or any type of conductive component of an electricaldevice. FIG. 6 shows substrate 605, back side 606 of substrate 605,heteroepitaxial layer 604, and patterned cap regions 602A followingpost-cap etch.

In some embodiments, ARC (703 in FIG. 7) may be applied over theheteroepitaxial layer 704. FIG. 7 shows substrate 705, back side 706 ofsubstrate 705, heteroepitaxial layer 704, ARC 703, and patterned capregions 702A following post-cap etch. Some embodiments may also employthe application of front side metal pads (801 in FIG. 8) and narrowmetal gridlines (not shown). At the end of front side processing, asemiconductor wafer with an unmodified substrate layer (806) can beobtained, as shown in FIG. 8. FIG. 8 shows substrate 805, back side 806of substrate 805, heteroepitaxial layer 804 overlying substrate 805, ARC803, patterned cap regions 802A, and front side metal pad 801electrically connected to patterned cap regions 802A.

In FIG. 9, the semiconductor wafer shown in FIG. 8 can be permanentlybonded to a cover glass 908 with an optically clear adhesive 907. Insome embodiments, the cover glass 908 may be space grade cover glass,which may be made of borosilicate glass. The back side of the substrate(806 in FIG. 8) can be thinned (909 in FIG. 9) by wet etching,back-grinding, or other methods. In some embodiments, the thinnedsubstrate 905 can be between 20 μm and 200 μm thick post-thinning.Thinned devices are desirable in some applications, for example, spacesolar cells. FIG. 9 shows thinned substrate 905, back side 909 ofthinned substrate 905, heteroepitaxial layer 904, ARC 903, patterned capregions (post-cap etch) 902A front side metal pad 901, optically dearadhesive 907, and cover glass 908,

In FIG. 10A, the back side 1009 of the substrate 1005 is patterned witha photosensitive polymer or any suitable type of suitable maskingmaterial in a desired TWV pattern (not shown), aligning TWV holes withfront side metal pads 1001 and patterned cap regions 1002A that end upforming a perimeter around the ARC-adjacent region of the TWV holes1010. Etching TWV holes 1010 starts from the back side 1009 of thesubstrate 1005 and, as shown in FIG. 10B, stops at the ARC layer 1003A.In some embodiments, the etchant mixture used can comprise a volumetricratio of 10% to 50% hydrochloric acid with a volumetric ratio of 10% to50% iodic acid in deionized water. The etchant mixture can have atemperature that ranges from 10° C. to 140° C. Etching stops at the ARC1003 that serves as a selective dielectric etch stop layer 1011. Then,the patterned photosensitive polymer/masking material (not shown) andthe ARC 1003 that is exposed in the TWV hole 1010 are removed. FIG. 10Aalso shows heteroepitaxial layer 1004, optically clear adhesive 1007,and cover glass 1008. FIG. 10B shows back side 1009 of substrate 1005,heteroepitaxial layer 1004, ARC layers 1003 and 1003A, patterned capregions 1002A, front side metal pad 1001, optical adhesive 1007, andcover glass 1008. Through-wafer via 1010 is wet etched down to ARC layer1003A and includes sidewalls 1010.

Suitable wet etchant mixtures comprising hydrochloric acid and iodicacid are disclosed, for example, in U.S. Application Publication No.2013/0312817, which is incorporated by reference in its entirety. Smoothsidewalls etched with the etchant mixture can comprise traces of iodine.The heteroepitaxial sidewalls can be characterized by a macroscopicallysmooth surface without significant undercutting and that continuouslywidens from the substrate to the ARC. In some embodiments, the etchantmixture used can comprise a volumetric ratio of 30% to 35% hydrochloricacid with a volumetric ratio of 14% to 19% iodic acid in deionizedwater. The etchant mixture can have a temperature that ranges from 30°C. to 45° C.

U.S. Application Publication No. 2015/0349181 to Fidaner et al.discloses a method of etching mesa sidewalls in multijunctionphotovoltaic cells using a single-step wet etch process, where theetchant comprises a mixture of hydrochloric acid and iodic acid, whichis incorporated by reference in its entirety. Fidaner demonstrates thatthe iodic etchant can be used to etch heteroepitaxial layers such ascharacteristic of multijunction photovoltaic cells having smoothsidewalls.

A wet etchant used to etch the TWVs can comprise iodic acid,hydrochloric acid, and water prepared in the molar ratios of 1:62:760,respectively. The molar ratios of iodic acid and hydrochloric acid canbe within, for example, a variance of ±5%, such that the molar ratios inthe mixture are within the ranges (0.95-1.05):(59-65) : 760, for iodicacid, hydrochloric acid, and water, respectively. The molar ratios ofiodic acid and hydrochloric acid can be within, for example, a varianceof ±10%, such that the molar ratios in the mixture are within the ranges(0.90-1.10):(56-68):760, for iodic acid, hydrochloric acid, and water,respectively. The molar ratios of iodic acid and hydrochloric acid canbe within, for example, a variance of ±15%, such that the molar ratiosin the mixture are within the ranges (0.85-1.15):(53-71):760, for iodicacid, hydrochloric acid, and water, respectively.

In terms of vol %, the iodic acid, hydrochloric acid and water can becombined in a 1:2:3 ratio by volume, wherein the aqueous solution ofhydrochloric acid can be 38%±3% by weight and the aqueous solution ofiodic acid can be 6.6%±1% by weight. The aqueous solution ofhydrochloric acid can be 38%±6% by weight and the aqueous solution ofiodic acid can be 6.6%±5% by weight. It is within the contemplation ofthe invention to use another solute or liquid mixtures besides water inthe wet etch process, although water is the most readily available.Similarly, other acids of different molar concentration can besubstituted for hydrochloric acid to yield the same result.

The wet etch results cross-sectional shape of the side wall profilecharacterized by a substantially macroscopically smooth curved profile,that is, having a substantially macroscopically smooth surface withoutsignificant undercutting of a junction region compared to other junctionregions.

The wet etchant can comprise a volumetric ratio of hydrochloric acidfrom 10%-50% and the volumetric ratio of iodic acid in the mixture canbe 10%-50%, where the aqueous solution of hydrochloric acid is 38%±3% byweight and the aqueous solution of iodic acid can be 6.6%±1.0% byweight, or 38%±5% by weight and the aqueous solution of iodic acid is6.6%±5.0% by weight. It is to be understood the same molar ratios of theconstituent chemicals can be provided using different volumetric ratioswith different molarities in the aqueous solutions used. Duringprocessing, the temperature of the wet etchant can be maintained between10° C. and 140° C., such as, for example, from 20° C. to 100° C., from20° C. to 60° C., or from 30° C. to 50° C.

A wet etchant can comprise volumetric ratio of hydrochloric acid from30% to 35% and a volumetric ratio of iodic acid from 14% to 19%, usingthe molarities in the aqueous solutions of the constituent chemicals,and the temperature of the mixture can be maintained between 30° C. and45° C. A wet etchant can comprise volumetric ratio of hydrochloric acidfrom 27% to 38% and a volumetric ratio of iodic acid from 11% to 22%,using the molarities in the aqueous solutions of the constituentchemicals, and the temperature of the mixture can be maintained between30° C. and 45° C.

FIG. 11 shows the result of the steps described with reference to FIGS.10A and 10B. Element 1112 is the exposed bottom of the front side metalpad 1101 after the ARC is removed from TWV hole 1110. The sidewalls 1010of the TWV holes (1010 and 1110) are smooth, as shown in FIG. 4B; thereis an absence of pitting (411) and rough sidewall surfaces that resultsusing prior art methods (FIG. 4A). There is also an absence of pittingon the back side (410) of the wet etched back-thinned substrate (1009and 1109) as shown in FIG. 4B—the semiconductor wafer is sufficientlyprotected by a photosensitive polymer/masking material (not shown) frometching that deviates from a desired etching pattern. The device shownin FIG. 4B includes cover glass 407, front side metal pad 406, patternedcap regions 404, ARC 405, heteroepitaxial layer 403, substrate 402, andback side surface 401 of substrate 402. The sidewalls 411 ofheteroepitaxial layer 411 are smooth, without pitting and with reducedundercutting. Also, not pitting 410 is present on the back side surface401 of substrate 402.

FIG. 11 shows front side metal pad 1101, patterned cap region (post-capetch) 1102A, ARC (dielectric) 1103, heteroepitaxial layer 1104,substrate 105, optically clear adhesive 1007, cover glass 1108, backsideof the wet etched back-thinned substrate 1109, TWV hole 1110, withsidewalls 1010, and exposed bottom of the front side metal pad 1112after TWV etch stop removal.

The ARC 1103A at the top of the TWV 1010 serves as an etch stop for thewet etch. After the wet etch and via formation the ARC at the top of theTWV can subsequently be removed, for example by dry etching or by wetetching using, for example, hydrofluoric acid, to expose front sidemetal pad 1112 (FIG. 11). Residual ARC 1109 can remain between thepatterned cap region 1102A and the TWV 1110. In certain embodiments, capregions may not be present and the metal pad may overly only the ARClayer. After wet etch and TWV formation, a portion or the entire ARClayer previously underlying the metal pad may be removed to expose thelower surface of the metal pad. If a portion of the ARC layer is removedthere will be an ARC layer between a portion of the metal pad and theheteroepitaxial layer.

The profiles shown FIG. 4A and FIG. 4B are for illustration purposes andother etch profiles may be characterized by other roughened and/orpitted surfaces. It is to be understood that the examples ofsemiconductor morphology illustrated in the present disclosure are notlimited to the substrate, heteroepitaxial and processing layers. It isknown to one skilled in the art that other embodiments may be present insemiconductor structures and devices.

As shown in FIG. 12, a passivation layer 1213 is applied over the backside 1209 of the wet etched back-thinned substrate according to adesired pattern to passivate the substrate 1205 from metal contact. Thepassivation layer 1213 also lines the walls of the TWV holes 1210. Thepassivation layer 1213 can be applied using standard depositiontechniques, including for example, photosensitive polymer application,plasma-enhanced chemical vapor deposition, atomic layer deposition, andelectrografting. In some embodiments, hard baking can be used in thisstep. The bottom 1212 of the front side metal pad 1201 remains exposedafter TWV etch stop removal. FIG. 12 shows front side metal pad 1201,patterned cap regions (post-cap etch) 1202A, ARC 1203, heteroepitaxiallayer 1204, substrate 1205, optically clear adhesive 1207, cover glass1208, back side 1209 of the wet etched back-thinned substrate, TWV hole1210, exposed bottom 1212 of the front side metal pad after TWV etchstop removal, and passivation layer 1213.

As shown in FIG. 13, substrate back side 1309 and TWV metal isolationresist pattern 1314 can be formed with a photosensitive polymer 1314)This patterning is carried out, for example, by photolithographytechniques which may or may not require hard baking, depending on thespecific embodiment. The bottom 1312 of the front side metal pad remainsexposed 1312. FIG. 13 shows front side metal pad 1301, patterned capregions (post-cap etch) 1302A, ARC 1303, heteroepitaxial layer 1304,substrate 1305, optically clear adhesive 1307, cover glass 1308, backside of the wet etched back-thinned substrate 11309, TWV hole 1310,exposed bottom 1312 of the front side metal pad after TWV retch stopremoval, passivation layer 1313, and back side and TWV metal isolationresist pattern 1314.

In FIG. 14, TWV metal 1415 is applied such that the TWV metal 1415 linesthe previously exposed bottom of the front side metal pad 1415 and linesthe sidewalls 1416 of TWV holes 1410, forming an electrical connectionto the TWV front side metal pad 1401. The TWV metal 1415 also lines aportion of the back side of the substrate (1417 and 1419), bounded bythe resist 1414 from previous the step (FIG. 13). In some embodiments,these TWV and back side substrate metals (1415, 1416, 1417 and 1419) canbe applied in a single deposition step. Sacrificial metal 1418 and metalisolation resist pattern 1414 are then lifted off to isolate positiveand negative electrical contacts, leading to the product shown in FIG.15.

FIG. 14 shows front side metal pad 1401, patterned cap regions (post-capetch) 1402A, ARC 1403, heteroepitaxial layer 1404, thinned substrate1405, optically clear adhesive 1407, and cover glass 1408, on the topside of the wet etched back-thinned substrate, TWV hole 1410, exposedbottom 1412 of the front side metal pad after TWV etch stop removalstep, passivation layer 1413, back side 1414 and TWV metal isolationresist pattern, TWV metal 1415 deposited on the bottom of the TWVinterconnecting directly to the top side metal pad, TWV metal 1416deposited along the sidewalls of the TWV isolated from theheteroepitaxial stack and the substrate by the passivation layer, TWVmetal 1417 deposited on the back side of the substrate, sacrificialmetal 1418 on top of the isolation resist, and back side metal 1419.

The completed TWV structure shown in FIG. 15 includes front side metalpad 1501, patterned cap regions (post-cap etch) 1502A, ARC 1503,residual ARC 1520, heteroepitaxial layer 1504, substrate 1505, opticallyclear adhesive 1507, cover glass 1508, TWV hole 1510, ARC layer 1503,TWV metal 1515 deposited on the bottom of the TWV (electrically connectsdirectly to the top side metal pad), TWV metal 1516 deposited along thesidewalls of the TWV isolated from the heteroepitaxial stack and thesubstrate by the passivation layer, TWV metal 1517 deposited on the backside of the substrate, and back side metal 1519.

A TWV can be, for example, from 20 μm to 50 μm deep, or from 10 μm to200 μm deep. A TWV can have a width, for example, from about 10 μm to500 u μm, from 10 μm to 400 μm, from 100 μm to 400 μm, or from 100 μm to250 μm. A TWV can be characterized, for example, by an aspect ratio from0.5 to 1.5 from 0.8 to 1.2, or from 0.9 to 1.1.

Referring to FIG. 15, depending on the width of the top of the TWVstructure, there can be a residual ARC layer 1503A or section between aportion of the front side metal 1501 and the heteroepitaxial layer 1504.The residual ARC layer 1503A can be between the patterned cap region1502A and the passivation layer 1513 on the sidewalls of the TWV. If thewidth of the top of the TWV structure is large, then there may not be aresidual ARC layer surrounding the top of the TWV within the patternedcap region. Passivation layer 1513 and ARC layer 1503 can comprise thesame or can have similar compositions. Passivation layer 1513 and ARClayer 1503 can comprise different compositions. For example, passivationlayer 1513 and ARC layer 1503 can comprise SiO₂, TiO₂, or a combinationthereof. Passivation layer 1513 and ARC layer 1503 can comprisematerials that minimize the mismatch in the coefficient of thermalexpansion (CTE) between the passivation layer and ARC layer and theunderlying and overlying layers. For example, the materials form thepassivation layer and/or ARC layer can be selected to minimize the CTEmismatch between the passivation layer and/or ARC layer and GaAs.

FIG. 16A and FIG. 16B each show a cross-section of a completed deviceviewed from the top of the semiconductor wafer and from the bottom ofthe semiconductor wafer, respectively. This device was manufactured bythe processes shown in FIGS. 5-15. FIG. 16A and FIG. 16B represent anexample of a particular embodiment and do not limit the presentdisclosure. Modifications in the processes and the resulting devices byone skilled in the art may result in final products with variations.Possible variations include device structure, shape, materials anddimensions. For example, although the patterned cap regions 1602A andfront side metal pad 1601 are shown to be annular, they are not limitedto this shape and represent only an embodiment of the presentdisclosure. Other shapes that may be used include, for example, squaresand rectangles.

In the example of a device that is manufactured by the processes shownin FIGS. 5-15, a front side metal pad lies directly over the TWV hole.In another example, where the processes are as described in FIGS. 17-27,a metal plug can be present in a device that is manufactured byprocesses shown in FIGS. 5 and 17-27, while a front side metal pad isabsent (not shown). The metal plug can be electrically conductive suchas gold, silver, copper, or an alloy of any of the foregoing. Otherelectrically conductive metals can also be used. The plug can fill theTWV or can comprise one or more layers of electrically conductivemetals. From the top side (FIG. 16A), the following components of thedevice are identified: front side metal pad 1601, patterned cap regions1602, ARC 1603 outside of patterned cap regions 1602, ARC 1603A withinpatterned cap regions 1602, passivation layer 1613 and TWV metal 1615that connects directly to the top side metal pad. From the bottom side(FIG. 16B), the following components of the device are identified:passivation layer 1613, TWV metal 1615 that connects directly to the topside metal pad, TWV metal 1616 along the sidewalls of the TWV isolatedfrom the heteroepitaxial layer and the substrate by the passivationlayer, TWV metal 1617 deposited on the back side of the substrate andback side metal 1619. These are examples of a particular embodiment anddo not limit the scope of the disclosure. Modifications in the methodand the device disclosed may result in final products with variations.The final product fabricated by methods in the disclosure will havesmooth sidewalls 411 instead of lateral undercutting and pitting of thesemiconductor wafer as shown, for example, in (FIGS. 4A and 4B). This isan advantageous improvement over prior art, resulting in improvedfabrication reliability and yield of devices that comprise aheteroepitaxial layer.

FIGS. 5 and 17-27 show an aspect of the invention that comprises etchingTWVs from the front side of a semiconductor wafer in the fabrication ofa back-contact solar cell. FIGS. 5 and 17-23 show steps associated withfront side processing, including the wet etch steps highlighted in thedisclosure. FIGS. 24-27 show steps involved in back side processing. Theprocess steps and final product described can be modified by one skilledin the art to accommodate a wide variety of semiconductor devices; thesteps and final product are not limited to solar cells. The processsteps illustrated in FIGS. 5 and 17-27 can be summarized as follows:FIG. 5 shows a heteroepitaxial layer on an unmodified substrate; FIG. 17shows a wafer after via hole lithography and wet etch; FIG. 18 shows awafer after contact cap layer patterning; FIG. 19 shows a wafer afterARC and passivation layer application, FIG. 20 shows a wafer afterpassivation layer removal from the bottom of TWV holes; FIG. 21 shows awafer after front side metal seed layer lithography and evaporation;FIG. 22 shows a wafer after gold plug lithography and electroplating;FIG. 23 shows a wafer after mounting on glass; FIG. 24 shows a waferafter back-grinding and wet etch back-thinning; FIG. 25 shows a waferafter back side passivation layer patterning and hard bake; and FIG. 26shows a wafer after back side and via-metal isolation lithography; andFIG. 27 shows a completed device after metal lift off (TWV metal andback side metal separation).

A semiconductor wafer (FIG. 5) can be provided comprising aheteroepitaxial layer 504 overlying the front side of the substrate 505,and a cap layer 502 overlying the front side of the heteroepitaxiallayer 504. The substrate includes back side 506. Materials used to formthe substrate include, for example, germanium, gallium arsenide,germanium alloys, and gallium arsenide alloys. Materials used to formthe heteroepitaxial layer include, for example, alloys of one or moreelements from group III and group V on the periodic table, such asindium gallium phosphide, indium phosphide, gallium arsenide, aluminumgallium arsenide, indium gallium arsenide, and dilute nitride compounds.The semiconductor wafer can undergo front side processing (FIGS. 5 and17-22). TWV holes (1707 in FIG. 17) can be formed by wet etching asdetermined by a photosensitive polymer pattern or any type of suitablemasking pattern (not shown). Etching of TWV holes 1707 starts from thefront side of the cap layer 1702, extends through heteroepitaxial layer1704, and stops at the substrate 1705 at any desired wafer depth beforethe wafer is etched completely through to the back side 1706. In someembodiments, the etchant mixture used is a volumetric ratio of 10% to50% hydrochloric acid with a volumetric ratio of 10% to 50% iodic acidand deionized water. The mixture has a temperature that ranges from 10°C. to 140° C. The patterned photosensitive polymer/masking material (notshown) can be removed.

After wet etching TWV holes (1807 in FIG. 18), patterned cap regions1802A are formed, guided by a photosensitive polymer pattern or any typeof suitable masking pattern (not shown). The patterned cap regions 1802Amay be patterned in a disk shape, but can also be patterned in a varietyof geometric configurations, as well as shaped to function as gridlines,busbars, pads and any type of conductive component of an electricaldevice. FIG. 18 shows patterned cap regions (post-cap etch) 1802A,heteroepitaxial layer 1804, substrate 1805, back side 1806 of thesubstrate, and TWV hole 1807.

In FIG. 19, ARC (1903, 1908) functions as a passivation layer after itis applied over the heteroepitaxial layer 1904, surrounding patternedcap regions 1902A and the TWV sidewalls of TWV hole 1907. Photosensitivepolymers can also be used as a passivation layer instead of an ARC. Thepassivation layer can be applied using standard deposition techniques,including for example, photosensitive polymer application,plasma-enhanced chemical vapor deposition, atomic layer deposition, andelectrografting. In some embodiments, hard baking is required in thisstep. FIG. 19 also shows substrate 1905 and back side 1906 of substrate1905.

In FIG. 20, the ARC or passivation layer is removed from the front sideof the bottom of the TWV hole 2007 to expose the front side 2009 of thewafer substrate that lies at the bottom of the TWV hole 2007. FIG. 20shows patterned cap regions (post-cap etch) 2002A, ARC 2003,heteroepitaxial layer 2004, substrate 2005, back side 2006 of thesubstrate, TWV hole 2007, ARC 2008, and exposed bottom 2009 of the viaafter removal of the passivation layer.

As shown in FIG. 21, metal is deposited from the front side of thesemiconductor wafer, such that a metal seed layer 2111 lines the TWVholes 2107 by overlying the TWV sidewalls, the bottom of the TWV 2112and the front side of the patterned cap regions 2102A and certaindesired areas of the ARC 2103 within the patterned cap region. Metaldeposition/metallization is guided by metal isolation resist pattern(not shown) that can be formed with a photosensitive polymer. Thispatterning can be carried out, for example, using standardphotolithography techniques which may or may not require hard baking,depending on the specific embodiment. In some embodiments, thismetallization step uses an evaporation method. The deposited metal seedlayer can function as a front side metal pad as well as a conductingmetal seed layer for electroplating the TWV sidewalls and the TWVbottom. Metal layer 2111 and 2112 represents a metal seed layer as wellas a metal layer after depositing metal to a certain thickness. FIG. 21shows patterned cap regions (post-cap etch) 2102A, ARC 2103,heteroepitaxial layer 2104, substrate 2105, back side 2106 of thesubstrate, TWV hole 2107, ARC 2108, front side metal 2110, metal seedlayer 2111 deposited along the sidewalls of the TWV isolated from theheteroepitaxial stack and the substrate by the passivation layer (ARC2108), and metal seed layer 2112 deposited on the bottom of the TWV2107.

As shown in FIG. 22, gold can be applied by lithography andelectroplating to form a gold plug 2213 in the TWVs, directly contactingthe metal seed layer deposited on the TWV bottom and sidewalls (2211,2212). The gold plug mechanically reinforces the TWV structure, allowingconduction of higher current density with low resistive losses. Otherelectrically conductive metals and alloys can be used to form plug 2213.FIG. 22 includes patterned cap regions (post-cap etch) 2202A, ARC 2203along the sidewalls of the TWV and overlying the heteroepitaxial layerwithin patterned cap regions 2202A, heteroepitaxial layer 2204,substrate 2205, backside 2206 of the substrate, TWV hole 2207, ARC 2208,front side metal 2210, metal seed/deposited metal layer 2211 depositedalong the sidewalls of the TWV isolated from the heteroepitaxial stackand the substrate by the passivation layer, metal seed layer/metal layer2212 deposited on the bottom of the TWV, and electroplated gold plug2213.

As shown in FIG. 23, the front side of the semiconductor wafer can bepermanently bonded to cover glass 2315 with an optically clear adhesive2314. In some embodiments, the cover glass may be space grade coverglass, which may be made of borosilicate glass. Now the semiconductorwafer is ready for further processing from the back side of the wafer.FIG. 23 includes patterned cap regions (post-cap etch) 2302A, ARC 2303,heteroepitaxial layer 2304, substrate 2305, back side 2306 of thesubstrate, TWV hole 2307, ARC 2308 overlying a portion of theheteroepitaxial layer within the patterned cap region, front side metal2310, metal seed layer 2311 deposited along the sidewalls of the TWVisolated from the heteroepitaxial stack and the substrate by thepassivation layer, metal seed layer 2312 deposited on the bottom of theTWV, electroplated gold plug 2313, optically clear adhesive 2314, andcover glass 2315.

As shown in FIG. 24, the back side of the substrate 2416 can be thinnedby wet etching, back-grinding, or other methods. In some embodiments,the substrate can be between 20 μm and 200 μm thick post-thinning.Thinned devices are desirable in some applications, including, forexample—space solar cells. The back side of the substrate can be thinnedto expose the bottom portion of the metal 2412 within the TWV. FIG. 24includes patterned cap regions (post-cap etch) 2402A, ARC 2403,heteroepitaxial layer 2404, substrate 2405, TWV hole 2407, ARC 2408,front side metal 2410, metal seed layer 2411 deposited along thesidewalls of the TWV isolated from the heteroepitaxial stack and thesubstrate by the passivation layer (ARC 2408), metal seed layer 2412deposited on the bottom of the TWV, electroplated gold plug 2413,optically clear adhesive 2414, cover glass 2415, and back side of thewet etched back-thinned substrate 2416.

As shown in FIG. 25, a passivation layer 2517 can be applied on the backside 2516 of the substrate 2505 according to a desired pattern topassivate the substrate from metal contact. The passivation layer 2508also lines the walls of the TWV holes. The passivation layer 2517 can beapplied using standard deposition techniques, including, for example,photosensitive polymer application, plasma-enhanced chemical vapordeposition, atomic layer deposition, and electrografting. In someembodiments, hard baking is required in this step. The bottom of thefront side metal pad 2512 remains exposed. FIG. 25 includes patternedcap regions (post-cap etch) 2502A, ARC 2503, heteroepitaxial layer 2504,substrate 2505, ARC 2508 along the sidewalls of the TWV and overlying aportion of the heteroepitaxial layer within the patterned cap regions,front side metal 2510, metal seed layer 2511 deposited along thesidewalls of the TWV isolated from the heteroepitaxial stack and thesubstrate by the passivation layer, metal seed layer 2512 deposited onthe bottom of the TWV, electroplated gold plug 2513, optically clearadhesive 2514, cover glass 2515, back side of the wet etchedback-thinned substrate 2516, and back side passivation layer 2517.

As shown in FIG. 26, back side and TWV metal isolation resist pattern2618 can be applied to determine the subsequent deposition of back sidemetal (2719 in FIG. 27) and TWV metal (2720 in FIG. 27). In someembodiments, these back side and TWV metals can be applied in a singledeposition step. FIG. 26 includes patterned cap regions (post-cap etch)2602A, ARC 2603, heteroepitaxial layer 2604, substrate 2605, TWV hole2607, ARC 2608, front side metal 2610, metal seed layer 2611 depositedalong the sidewalls of the TWV isolated from the heteroepitaxial stackand the substrate by the passivation layer, metal seed layer 2612deposited on the bottom of the TWV, electroplated gold plug 2613,optically clear adhesive 2614, cover glass 2615, back side of the wetetched back-thinned substrate 2616, passivation layer 2617, and backside and TWV metal isolation resist pattern 2618.

FIG. 27 shows a completed device after the back side sacrificial metaland the metal isolation resist pattern are lifted off to isolatepositive and negative electrical contacts. FIG. 27 shows patterned capregions (post-cap etch) 2702A, ARC 2703, heteroepitaxial layer 2704,substrate 2705, TWV hole 2707, ARC 2708, front side metal 2710, metalseed layer 2711 deposited along the sidewalls of the TWV isolated fromthe heteroepitaxial stack and the substrate by the passivation layer,metal seed layer 2712 deposited on the bottom of the TWV, electroplatedgold plug 2713, optically clear adhesive 2714, cover glass 2715,passivation layer 2717, back side metal 2719, and TWV metal 2720deposited on the back side of the semiconductor wafer.

In an aspect of the invention, a method of forming a semiconductordevice comprises the steps of: providing a semiconductor wafer, whereinthe semiconductor wafer comprises: a substrate region comprising a frontside and a back side; a heteroepitaxial layer overlying the front sideof the substrate region, wherein, the heteroepitaxial layer comprises afirst subcell and at least one additional subcell overlying the firstsubcell; and at least one of the first subcell or the at least oneadditional subcell comprises an alloy comprising one or more elementsfrom group III of the periodic table, N, As, and an element selectedfrom Sb, Bi and a combination thereof; a plurality of patterned capregions overlying the heteroepitaxial layer; an anti-reflective coatingoverlying the heteroepitaxial layer; and; a corresponding metal regionoverlying each of the plurality of patterned cap regions; bonding acover glass to the front side of the semiconductor wafer with anoptically clear adhesive; removing a desired amount from thesemiconductor wafer by a thinning of the substrate region from the backside of the semiconductor wafer; patterning the back side of thesemiconductor wafer with a back etch through-wafer via pattern; etchingfrom the back side of the semiconductor wafer a plurality ofthrough-wafer vias using a single wet etchant mixture, wherein each ofthe plurality of through-wafer vias extends from the back side of thesemiconductor wafer to the anti-reflective coating overlying theheteroepitaxial layer; removing the anti-reflective coating to expose abottom side of the corresponding metal region with a subsequent wetetching method, wherein the subsequent wet etching method is specificfor the removal of the anti-reflective coating; depositing a passivationlayer on the through-wafer via walls with standard depositiontechniques; depositing a resist pattern on the back side of thesemiconductor wafer for back side metal isolation, wherein the resistpattern underlies the passivation layer; depositing a metal on the backside of the semiconductor wafer and on the through-wafer via; andremoving the resist pattern and a sacrificial metal.

In an aspect of the invention, a method of forming a semiconductordevice comprises the steps of: providing a semiconductor wafer, whereinthe semiconductor wafer comprises: a substrate region comprising a frontside and a back side; a heteroepitaxial layer overlying the front sideof the substrate region, wherein, the heteroepitaxial layer comprises afirst subcell and an at least one additional subcell overlying the firstsubcell; at least one subcell comprises an alloy comprising one or moreelements from group III of the periodic table, N, As, and an elementselected from Sb, Bi and a combination thereof; and a cap layeroverlying the heteroepitaxial layer; patterning the front side of thesemiconductor wafer with a front etch through-wafer via pattern; etchingfrom the front side of the semiconductor wafer a plurality ofthrough-wafer vias using a single wet etchant mixture, wherein, each ofthe plurality of through-wafer vias extends from the front side surfaceof the semiconductor wafer into the substrate; patterning the pluralityof patterned cap regions on the heteroepitaxial layer on the front sideof the semiconductor wafer; depositing an anti-reflective coatingoverlying the heteroepitaxial layer and the through-wafer via sidewalls;removing, from the front side, the anti-reflective coating from thebottom of the through-wafer via holes; depositing a front side resistpattern from the front side of the semiconductor wafer, wherein thefront side resist pattern guides metal layer lithography; and depositinga metal on the front side of the semiconductor wafer, on thethrough-wafer via sidewalls and on the through-wafer via bottom.

In any of the preceding aspects, the anti-reflective coating is apassivation layer.

In any of the preceding aspects, the passivation layer comprisesphotosensitive polymers.

In any of the preceding aspects, the wet etchant mixture comprises: avolumetric ratio of hydrochloric acid of 10% to 50%; volumetric ratio ofiodic acid of 10% to 50%; and deionized water, wherein the single wetetchant mixture has a temperature of 10° C. to 140° C.

In any of the preceding aspects, the back etch through-wafer via patternand the front etch through-wafer via pattern is formed using aphotoresist, using a hard mask, or using both a photoresist and a hardmask.

In any of the preceding aspects, wherein the semiconductor devicecomprises a solar cell.

In any of the preceding aspects, the semiconductor device comprises asolar cell or a back-contact solar cell.

In any of the preceding aspects, the method further comprises fillingeach of the plurality of through-wafer vias with gold.

In any of the preceding aspects, the method further comprises: bonding acover glass to the front side surface of the semiconductor wafer with anoptically clear adhesive; removing a desired amount of the semiconductorwafer by a thinning of the substrate region from the back side of thesemiconductor wafer; depositing a passivation layer with standarddeposition techniques or lithography on the back side of thesemiconductor wafer, wherein the passivation layer is guided by apassivation layer pattern; depositing a back side metal isolation resistpattern on the back side of the semiconductor, wherein the back sidemetal isolation resist pattern underlies the passivation layerdepositing a metal on the back side of the semiconductor wafer; andremoving the back side metal isolation resist pattern and a sacrificialmetal.

In any of the preceding aspects, the thinning of the substrate regionfrom the back side of the semiconductor wafer is achieved by wetetching, back-grinding or substrate lift-off, or any combination ofthese methods.

In an aspect of the invention, a semiconductor device comprises: aheteroepitaxial layer, further comprising an alloy comprising one ormore elements from group III of the periodic table, N, As, and anelement selected from Sb, Bi and a combination thereof; and a pluralityof through-wafer vias characterized by the absence of pitting on smoothsidewall surfaces formed by the method of any of the preceding aspectsof the invention.

In any of the preceding aspects, the heteroepitaxial layer comprisesGa_(1-x)In_(x)N_(y)As_(1-y-z)Sb_(z); and the content values for x, y,and z are within composition ranges as follows: 0.03≤x≤0.22,0.007≤y≤0.055 and 0.001≤z≤0.05.

In any of the preceding aspects, the semiconductor device is aback-contact multijunction photovoltaic cell.

In an aspect of the invention, a through-wafer via structure comprises:a substrate comprising a back side and a front side; a heteroepitaxiallayer overlying the front side of the substrate; an antireflectioncoating overlying a first portion of the heteroepitaxial layer; apatterned cap region overlying a second portion of the heteroepitaxiallayer; a front side metal pad overlying and electrically connected tothe patterned cap region, wherein the front side metal pad comprises abottom surface; and a through-wafer via extending from the back side ofthe substrate to the front side metal pad, wherein the through-wafer viacomprises sidewalls; a passivation layer overlying a portion of the backside of the substrate and the sidewalls of the through-wafer via; and ametal layer overlying the passivation layer and the bottom surface ofthe front side metal pad within the through-wafer via.

In any of the preceding aspects, the heteroepitaxial layer comprises oneor more elements from group III of the periodic table, N, As, and anelement selected from Sb, Bi and a combination thereof.

In any of the preceding aspects, the heteroepitaxial layer comprises oneor more subcells of a multijunction solar cell, wherein at least one ofthe subcells comprises one or more elements from group III of theperiodic table, N, As, and an element selected from Sb, Bi and acombination thereof.

In any of the preceding aspects, the through-wafer via is characterizedby smooth sidewall surfaces and the back side of the substrate is freeof pitting.

In an aspect of the invention, a semiconductor device comprises thethrough-wafer via structure according to any of the preceding aspects ofthe invention.

In an aspect of the invention, a through-wafer via structure comprises:a substrate comprising a back side and a front side; a heteroepitaxiallayer overlying the front side of the substrate; an anti-reflectioncoating overlying a first portion of the heteroepitaxial layer; apatterned cap region overlying a second portion of the heteroepitaxiallayer; a front side metal overlying a portion of the anti-reflectioncoating and the patterned cap region; a through-wafer via extending fromthe back side of the substrate through a portion of the anti-reflectioncoating; a passivation layer overlying side walls of the through-wafervia; a metal seed layer overlying the passivation layer and plugging thebottom of the through-wafer via; and a metal overlying the metal seedlayer and filling the through-wafer via.

In any of the preceding aspects, the heteroepitaxial layer comprises oneor more elements from group III of the periodic table, N, As, and anelement selected from Sb, Bi and a combination thereof.

In any of the preceding aspects, the heteroepitaxial layer comprises oneor more subcells of a multijunction solar cell, wherein at least one ofthe subcells comprises one or more elements from group III of theperiodic table, N, As, and an element selected from Sb, Bi and acombination thereof.

In any of the preceding aspects, the through-wafer via is characterizedby smooth sidewall surfaces and the back side of the substrate is freeof pitting.

In an aspect of the invention, a semiconductor device comprising thethrough-wafer via structure according to any of the preceding aspects.

According to an aspect of the invention, a through-wafer via structurecomprises: a substrate having a front substrate surface and a backsubstrate surface; a heteroepitaxial layer overlying the front substratesurface; a front surface contact overlying a portion of and electricallyconnected to the heteroepitaxial layer; an optical adhesive overlyingthe front surface contact and the heteroepitaxial layer; a coverglassoverlying the optical adhesive; a back surface solder pad underlying aportion of and electrically connected to the back substrate surface; afront surface solder pad underlying and insulated from the backsubstrate surface; and a through-wafer-via interconnecting the frontsurface solder pad and the front surface contact.

According to any of the preceding aspects, the substrate is less than150 μm thick.

According to any of the preceding aspects, the heteroepitaxial layercomprises at least two junctions of a multijunction solar cell.

According to any of the preceding aspects, the method further comprises:an antireflection coating overlying a first portion of theheteroepitaxial layer; a patterned cap region overlying a second portionof the heteroepitaxial layer; a front side metal pad overlying andelectrically connected to the patterned cap region, wherein the frontside metal pad comprises a bottom surface; and a through-wafer-viaextending from the back substrate surface to the front side metal pad,wherein the through-wafer-via comprises sidewalls; a passivation layeroverlying a portion of the back substrate surface and the sidewalls ofthe through-wafer-via; and a metal layer underlying the passivationlayer and the bottom surface of the front side metal pad within thethrough-wafer-via.

According to any of the preceding aspects, the through-wafer-via ischaracterized by smooth sidewall surfaces and the back substrate surfaceis free of pitting.

According to any of the preceding aspects, the method further comprises:an anti-reflection coating underlying a first portion of theheteroepitaxial layer; a patterned cap region overlying a second portionof the heteroepitaxial layer; a front side metal overlying a portion ofthe anti-reflection coating and the patterned cap region; athrough-wafer via extending from the back substrate surface through aportion of the anti-reflection coating; a passivation layer overlyingside walls of the through-wafer-via; a metal layer overlying thepassivation layer and plugging the bottom of the through-wafer via; anda metal overlying the metal layer and filling the through-wafer-via.

According to any of the preceding aspects, the method further comprisesan anti-reflection coating layer between a portion of the front sidemetal and the heteroepitaxial layer.

According to any of the preceding aspects, the method further comprisesan anti-reflection coating layer between a portion of the through wafervia sidewall and the patterned cap region.

According to an aspect of the invention, a semiconductor devicecomprises a plurality of the through wafer via structures according tothe invention.

According to any of the preceding aspects, the semiconductor device ischaracterized by a unit mass per area of less than 0.09 g/cm².

According to an aspect of the invention, a method of fabricating athrough wafer via structure, comprises: providing a semiconductor wafer,wherein the semiconductor wafer comprises: a substrate comprising afront substrate surface and a back substrate surface; a heteroepitaxiallayer overlying the front substrate surface; a front surface contactoverlying and electrically connected to a portion of the heteroepitaxiallayer; an optical adhesive overlying the front surface contact and theheteroepitaxial layer; and a coverglass overlying the optical adhesivelayer; and thinning the substrate.

According to any of the preceding aspects, the method further comprises,forming a through-wafer-via interconnecting the front surface contact toa front contact pad underlying the back substrate surface.

According to any of the preceding aspects, forming a through-wafer-viacomprises wet etching using an etchant mixture comprising iodic acid,hydrofluoric acid, and water.

According to any of the preceding aspects, the method further comprisesforming a back surface contact interconnected to the back substratesurface.

According to any of the preceding aspects, thinning the substratecomprises wet etching, back-grinding, lift-off, or any combination ofany of the foregoing.

According to any of the preceding aspects, the heteroepitaxial layercomprises at least two junctions of a multijunction solar cell.

According to an aspect of the invention, a through wafer via structurecomprises: a substrate having a front substrate surface and a backsubstrate surface; a heteroepitaxial layer overlying the front substratesurface; a front surface contact overlying a portion of and electricallyconnected to the heteroepitaxial layer; an optical adhesive overlyingthe front surface contact and the heteroepitaxial layer; a coverglassoverlying the optical adhesive; a passivation layer underlying a portionof the back substrate surface; a back metal pad underlying a portion ofthe passivation layer; a through-wafer-via electrically interconnectingthe front metal contact and the back metal pad; and a backside metalelectrically connected to the back substrate surface.

According to any of the preceding aspects, a through-wafer via structurefurther comprises a patterned cap region overlying a portion of theheteroepitaxial layer; and an antireflection coating overlying a portionof the heteroepitaxial layer; wherein the front surface contact overliesthe patterned cap region and is electrically connected to the patternedcap region.

According to any of the preceding aspects, the antireflection coatingoverlies the heteroepitaxial within the patterned cap region; and theantireflection coating overlies the sidewalls of the through-wafer-via.

According to any of the preceding aspects, the substrate is less than150 μm thick.

According to any of the preceding aspects, the heteroepitaxial layercomprises at least two junctions of a multijunction solar cell.

According to any of the preceding aspects, the through-wafer viastructure comprises a gold plug filling the through-wafer via.

According to an aspect of the invention, a semiconductor devicecomprises a plurality of the through wafer via structures according tothe invention.

According to any of the preceding aspects, the semiconductor device ischaracterized by a unit mass per area of less than 0.09 g/cm².

According to an aspect of the invention, a method of fabricating athrough wafer via structure comprises: providing a semiconductor wafer,wherein the semiconductor wafer comprises: a substrate having a frontsubstrate surface and a back substrate surface; a heteroepitaxial layeroverlying the front substrate surface; and a patterned cap regionoverlying a first portion of the heteroepitaxial layer; etching athrough-wafer-via extending from the heteroepitaxial layer to within thesubstrate; depositing an antireflection coating on a second portion ofthe heteroepitaxial layer and on a sidewall and a bottom of thethrough-wafer-via; etching the antireflection coating on the bottom ofthe through-wafer-via to expose the substrate; depositing a frontsurface contact overlying at least a portion of the patterned capregion, the antireflection coating within the patterned cap region, thesidewalls of the through-wafer-via, and the bottom of thethrough-wafer-via; applying an optical adhesive overlying the frontsurface contact, the patterned cap region, and the antireflectioncoating; applying a coverglass overlying the optical adhesive; andthinning the substrate.

According to any of the preceding aspects, the heteroepitaxial layercomprises at least two junctions of a multijunction solar cell.

According to any of the preceding aspects, etching a through-wafer-viacomprises wet etching using an etchant mixture comprising iodic acid,hydrofluoric acid, and water.

According to any of the preceding aspects, thinning the substratecomprises exposing the front surface contact at the bottom of thethrough-wafer-via.

According to any of the preceding aspects, thinning the substratecomprises wet etching, back-grinding, lift-off, or any combination ofany of the foregoing.

There are alternative ways of implementing the embodiments disclosedherein. Accordingly, the present embodiments are to be considered asillustrative and not restrictive. Furthermore, the claims are not to belimited to the details given herein, and are entitled their full scopeand equivalents thereof.

What is claimed is:
 1. A through wafer via structure, comprising: asubstrate having a front substrate surface and a back substrate surface;a plurality of heteroepitaxial layers overlying the front substratesurface, wherein the plurality of heteroepitaxial layers comprises a topheteroepitaxial surface; a first antireflection coating overlying afirst portion of the plurality of heteroepitaxial layer; a patterned capregion overlying a second portion of the plurality of heteroepitaxiallayers and electrically connected to the plurality of heteroepitaxiallayers; a through-wafer-via disposed within the patterned cap region andextending from top heteroepitaxial surface to the back substratesurface, wherein the through-wafer-via comprises a sidewall; a secondantireflection coating overlying a third portion of the plurality ofheteroepitaxial layers and overlying the sidewall of thethrough-wafer-via; a front side metal overlying the patterned cap regionand the second antireflection coating; an optical adhesive overlying thefirst antireflection coating, the patterned cap region, the front sidemetal; and a coverglass overlying the optical adhesive.
 2. Thethrough-wafer via structure of claim 1, comprising a metal plugoverlying the second antireflection coating within thethrough-wafer-via, and wherein the optical adhesive overlies the metalgold plug.
 3. The through-wafer via structure of claim 1, comprising agold plug overlying the second antireflection coating within thethrough-wafer-via, and wherein the optical adhesive overlies the metalplug.
 4. The through-wafer via structure of claim 1, comprising: apassivation liner underlying a first portion of the back substratesurface and contacting the second antireflection coating; a frontsurface metal pad underlying the passivation liner and electricallyconnected to the front side metal; and a back side metal underlying asecond portion of the back substrate surface.
 5. The through-wafer viastructure of claim 1, wherein the substrate is less than 150 μm thick.6. The through-wafer via structure of claim 1, wherein the plurality ofheteroepitaxial layers comprises at least two junctions of amultijunction solar cell.
 7. A semiconductor device comprising aplurality of the through-wafer-via structures of claim
 1. 8. Thesemiconductor device of claim 7, wherein the semiconductor devicecomprises a surface mount device.
 9. The semiconductor device of claim7, wherein the semiconductor device is characterized by a unit mass perarea of less than 0.09 g/cm².
 10. The semiconductor device of claim 7,wherein the semiconductor device comprises a multijunction photovoltaiccell.
 11. A photovoltaic module comprising a plurality of the surfacemount multijunction photovoltaic cells of claim
 10. 12. The photovoltaicmodule of claim 10, wherein the photovoltaic module comprises: a frontsurface area; and the plurality of surface mount multijunctionphotovoltaic cells cover at least 70% of the front surface area.
 13. Apower system comprising at least one photovoltaic module of claim 10.14. A method of fabricating a through-wafer-via structure, comprising:providing a semiconductor wafer, wherein the semiconductor wafercomprises: a substrate having a front substrate surface and a backsubstrate surface; a plurality of heteroepitaxial layers overlying thefront substrate surface; an antireflection coating overlying a firstportion of the plurality of heteroepitaxial layers; a patterned capregion overlying a second portion of the plurality of heteroepitaxiallayers and electrically connected to the plurality of heteroepitaxiallayers; a via extending from the plurality of heteroepitaxial layers towithin the substrate, wherein the via comprises a sidewall; theantireflection coating overlying a third portion of the plurality ofheteroepitaxial layers and the via sidewall; a front side metaloverlying the patterned cap region and the antireflection coatingoverlying the third portion of the plurality of heteroepitaxial layersand the via sidewall; and an optical adhesive overlying theantireflection coating, the patterned cap region, and the front sidemetal; a coverglass overlying the optical adhesive; and thinning thesubstrate to expose the front side metal at the bottom of the via.
 15. Amethod of fabricating a through wafer via structure, comprising:providing a semiconductor wafer, wherein the semiconductor wafercomprises: a substrate having a front substrate surface and a backsubstrate surface; a plurality of heteroepitaxial layers overlying thefront substrate surface; and a cap layer overlying a first portion ofthe plurality of heteroepitaxial layer; etching a via extending from thecap layer to within the substrate, wherein the via comprises a sidewall;etching the cap layer to provide a patterned cap region overlying afirst portion of the plurality of heteroepitaxial layers; depositing anantireflection coating overlying a second portion of the plurality ofheteroepitaxial layers, overlying a third portion of the plurality ofheteroepitaxial layers, overlying the sidewall of the through-wafer-via,and overlying the substrate at the bottom of the via; etching theantireflection coating on the bottom of the via to expose the substrate;depositing a front surface contact overlying at least a portion of thepatterned cap region, overlying a third portion of the plurality ofheteroepitaxial layers, the sidewall of the via, and the bottom of thevia; applying an optical adhesive overlying the front surface contact,the patterned cap region, and the antireflection coating; applying acoverglass overlying the optical adhesive; and thinning the substrate toexpose the front surface contact at the bottom of the via.
 16. Themethod of claim 15, wherein after the depositing the front surfacecontact, depositing a metal plug within the via.
 17. The method of claim15, comprising: depositing a passivation liner underlying a firstportion of the back substrate surface and contacting the antireflectioncoating on the via sidewall; depositing front surface metal padunderlying the passivation liner and electrically connected to the frontsurface metal; and depositing a back side metal on a second portion ofthe back substrate surface.
 18. The method of claim 15, wherein theplurality of heteroepitaxial layers comprises at least two junctions ofa multijunction solar cell.
 19. The method of claim 15, wherein etchinga via comprises wet etching using an etchant mixture comprising iodicacid, hydrofluoric acid, and water.
 20. The method of claim 15, whereinthinning the substrate comprises exposing the front surface contact atthe bottom of the via.
 21. The method of claim 15, wherein thinning thesubstrate comprises wet etching, back-grinding, lift-off, or anycombination of any of the foregoing.
 22. A semiconductor devicecomprising a through-wafer-via structure fabricated by the method ofclaim
 15. 23. The semiconductor device of claim 22, wherein thesemiconductor device comprises a surface mount device.
 24. Thesemiconductor device of claim 22, wherein the semiconductor devicecomprises a multijunction photovoltaic cell.
 25. A photovoltaic modulecomprising a plurality of the semiconductor devices of claim
 24. 26. Thephotovoltaic module of claim 25, wherein the photovoltaic modulecomprises: a front surface area; and the plurality of surface mountmultijunction photovoltaic cells cover at least 70% of the front surfacearea.
 27. A power system comprising at least one photovoltaic module ofclaim 25.